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Ayush Srivastava

Interactive resume

Profile

I'm a Master Student at IIT Gandhinagar in the discipline of Electrical Engineering.My area of specialization is Microelectronics and VLSI Design.


About me

I am an allround semiconductor guy. I have good knowledge of Digital System Design, VLSI Design, Semiconductor device Physics , Verilog, Python, C. My area of Interest are Memory Design, Emerging Devices for Digital Circuits, Machine learning assisted CAD tools, Low Power VLSI Design, In Memory Computing, Logic in Memory devices, Computer Architecture, Chip Design and verification. I am a Hardworking, Honest and Dedicated person.I love spending time on fixing things which does not work.I like working in teams, you'll learn faster and much more. As the saying goes: 'two heads are better than one'.

Ayush Srivastava

Details

Name:
Ayush Srivastava
Age:
22 years
Location:
'Duven Hostel Room no-436,IIT Gandhinagar,382055,Gujarat,India.

Education

“Protons give an atom its identity, electrons its personality.”
- Bill Bryson, A short history of nearly everything


IIT Gandhinagar

July 2021 - Present

MTech-Microelectronics and VLSI Design Course-VLSI Design,Semiconductor Devices,Physics of Transistor, Analog IC Design.

NIT Mizoram

Aug 2017 - Jun 2021

BTech-Electronics and Communication Engineering Course-Digital Electronics, Analog Electronics, Nanoelectronics,Computer Organisation and Operating System, Data Structure, C.


Abilities

“Life without knowledge is death in disguise.”
- Talib Kweli


Skills

  • Verilog
  • C Programming
  • Python
  • HTML
  • CSS
  • Object Orientated Programming

Languages

  • Hindi
  • English

Tools

  • Xillnx Vivado
  • Silvaco TCAD
  • Cadence Virtuoso
  • PyCharm

Projects/Internships

“Fear is a real killer. I try to trudge through the jungle with as little fear as possible.”
- William Shockley


IIT Gandhinagar

October 2021 - November 2021

Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM under the supervision of Prof. Joycee Mekkie.

In this project we have implemented various technics towards reliable and high-speed 6T CSRAM.We also have designed and simulated sense amplifier for roboust and fast sensing.We have done pre and postlayout analysis.

NIT Mizoram

Aug 2020 - May 2021

Design and Simulation of 14 nm SOI FinFet under the supervision of Dr. R.S Dhar.

In this project I have Designed and Simulated 14nm n channel SOI FinFET on Silvaco TCAD.Optimized various SCE such as DIBL, Ion/Ioff by varying gate work function of device.Published a paper as a first author in IEEE DevIC 2021.

Publication


Ayush Srivastava, Swagat Nanda, Serto Engneichung Aimol, Rudra Sankar Dhar” Parametric Analysis for Varied Gate Work function in Trigate n-channel FinFET” at IEEE 2021 4th International Conference Devices for Integrated Circuit (DevIC).

Link- https://ieeexplore.ieee.org/document/9455803

Awards


1.Department Gold Medalist.

2.IEEE 5th International Test Conference India Full Fellowship.(July 2021)

Contact

“If I had asked people what they wanted, they would have said faster horses. ”
- Henry Ford